Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization

The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits its smallest standby leakage current its power gating can achieve. In this paper, we point out that, in the high-level synthesis of a nonzero clock skew circuit, the resource binding (including functional units and registers) has a large impact on the maximum allowable delays of functional units; as a result, different resource binding solutions have different standby leakage currents. Based on that observation, we present the first work formulating the timing driven power gating in high-level synthesis. Given a target clock period and design constraints, our goal is to derive the minimum-standby-leakage-current resource binding solution. Benchmark data show that, compared with the existing design flow, our approach can greatly reduce the standby leakage current without any overhead.