Floating accumulator architecture

نویسندگان

  • Yuan-Shin Hwang
  • Wei-Che Hsu
چکیده

Although technology advancement can pack more and more physical registers in processors, the numbers of architectured registers defined by the instruction set architectures (ISAs) remain relatively small on most modern processors. Exposing more architectured registers to compilers and programmers can improve the effectiveness of compiler optimization and the quality of code. However, increasing the number of architectured registers by simply adding extra bits to the register fields of instructions will expand the code size. Therefore, a better way of exposing more ISA registers without significantly expanding the code size is needed. This paper presents a new ISA called Floating Accumulator Architecture (FAA) that can expand the number of ISA registers without increasing the instruction length. Unlike the accumulator architecture whose accumulator is a fixed, special register, FAA dynamically chooses a register from the general-purpose register file as the accumulator. Since the accumulator implicitly stores the result, the destination register field can be omitted from FAA instructions, resulting in a saving of 3 to 5 bits for each instruction. This new free instruction bit space can be utilized to double the number of ISA registers of modern 32-bit RISC processors.

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عنوان ژورنال:
  • Microprocessors and Microsystems - Embedded Hardware Design

دوره 51  شماره 

صفحات  -

تاریخ انتشار 2017