The Ieee Verilog-2001 Simulation Tool Scoreboard

Verilog-2001 added many valuable enhancements to the IEEE1364-1995 Verilog Standard, but when can we safely use them? When the full suite of tools used by your company to do design all support Verilog-2001 enhancements, your company can safely start taking advantage of the enhancements. This paper details a number Verilog-2001 coding examples and indicates which simulation tools support the enhancement. This paper is not intended to run performance benchmarks against the different simulation vendors and indeed does not include performance data. This paper is intended to inform the Verilog design and synthesis community which Verilog-2001 enhancements have been implemented by the various vendors so that the end-user can scan the list of vendors for implemented enhancements to determine when their company can start coding with the enhanced Verilog-2001 coding styles. This paper includes multiple "scorecards" (tables) to show which simulation vendors support the important Verilog-2001 enhancements. The latest version of tools from major EDA vendors are represented on the "scorecards." 1.0 Introduction The IEEE Verilog-2001 Standard introduced a number of enhancements intended to make designs more concise and more powerful. Stuart Sutherland has published a book on Verilog-2001 enhancements and ordered those enhancements by number. This paper re-orders the enhancements, according to user requested priorities and RTL-coding partitions, but I do cross reference the enhancements discussed in this paper with the enhancement numbers as reported in Sutherland's book for easy correlation. At the time that this paper went to publication, I was not done testing as much as I had wanted. This paper will continue to be updated and readers are encouraged to go to the Sunburst Design web page referenced at the end of this paper to download copies of this paper with updated information.