Analysis of Leakage Current and SNM For 7T SRAM Cell in Nanometre Era

: In the microprocessors world SRAM play a vital role, but as the technology is scaling in nanometer, leakage current and leakage power both are the most known problems for SRAM cells in low power applications. More than 40% of the total power of the SRAM is waste due to the leakage through transistor. This paper compares the working, performance and results of two different SRAM topologies; a conventional 6T SRAM cell and a proposed 7T SRAM cell. Because of the direct paths through bit-line (BL) to their storage node, the conventional 6T SRAM cell suffered from external noise margin. But in the case of 7T SRAM cell there are two separate mechanisms for the data; one is for write the data and another one for read the stored data. Here we examined the difference between the power consumption of both 6T and 7T SRAM cell and also find out which cell works better on low power. Keywords—: leakage power, leakage current and NMOS, PMOS, SRAM static noise margin.