Low-power Floating-point Encoding for Signal Processing Applications

IEEE organization defined a standard for floatingpoint arithmetic, used by processing systems, in its directive 754 [1]. This directive encodes floatingpoint numbers using a maximum of 64 bits: 23 bit of fractional as single precision format and 52 bit of fractional as double precision format. The new multimedia terminals require low-power applications; the most important floating-point units (adders and multipliers) represent a significant part of total power wasted by a modern System-OnChip. They might dissipate less power, using a reduced format representation. To verify this possibility, real systems simulate floating point operations using different formats. In this conference paper, multimedia systems operate in different scenarios: wireless communication and image manipulation. 1 1Copyright 2003 IEEE. Published in The IEEE 2003 Workshop on Signal Processing Systems (SIPS’03)scheduled for August 27-29, 2003 in Seoul, Korea. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE. Contact: Manager, Copyrights and Permissions / IEEE Service Center / 445 Hoes Lane / P.O. Box 1331 / Piscataway, NJ 08855-1331, USA. Telephone: + Intl. 908-562-3966.