Noise Properties of CMOS Current Conveyors

The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class A B implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current sources, and with the class A B design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current.