Evaluation of dynamic branch predictors for modern ILP processors

Modern instruction-level parallel (ILP) processors use superscalar architectures with deep pipelines in order to execute multiple instructions per cycle. The frequency and behavior of branch instructions seriously hinder performance of ILP processors. Various mechanisms, both at the compiler, as well as the processor level, have been proposed to predict the branch behavior. This work investigates various dynamic branch predictors at processor level to do a fair comparison among them. An experimental framework has been described using eight SPECint95 benchmarks and similar key parameters for evaluating these predictors. The performance impact of branch misprediction, the instruction-window size, machine width, the predictor size, ®rst-level instruction-cache size, and history register length has been investigated. The hardware cost effectiveness of the different schemes is discussed.