Simplified Parallel Architecture for LTE-A Turbo Decoder Implemented on FPGA

This paper describes a turbo decoder for 3GPP Long Term Evolution Advanced (LTE-A) standard, using a Max LOG MAP algorithm, implemented on Field Programmable Gate Array (FPGA). Taking advantage of the quadratic permutation polynomial (QPP) interleaver proprieties and considering some FPGA block memory characteristics, a simplified parallel decoding architecture is proposed. It should be used especially for large data blocks, when high decoding latency is introduced by the serial decoding. The parallelization factor N is usually a power of 2, the maximum considered value being 8. The obtained parallel decoding latency is N times lower than the serial decoding latency. With the cost of very low latency added to this value, the parallel decoding performances are similar with the serial decoding ones. The novelty of the proposed parallel architecture is that only one interleaver is used, independently of the N value. Key-Words: LTE-A, turbo decoder, Max LOG MAP, parallel architecture, FPGA