Design of 1024*16 Cm8 Ultra Low Voltage Sram with Self Time Power Reduction Technique

Technology scaling has enabled us to integrate both memory and logic circuits on a single chip. However, the performance of embedded memory and especially SRAM (Static Random Access Memory) that is widely used in the industry as on the on-chip memory cache in ultra low voltage applications can adversely affect the speed and power efficiency of the overall system. This report discusses the design techniques to realize input/output circuits which are used to access SRAM cell based memory array in ultra low voltage applications, to overcome the cell’s variations. It also explains the variability problems in a SRAM bit-cell and many approaches to address them. The column decoder/multiplexer, the write driver circuit, the data output circuit, and the sense amplifier is discussed and implemented at transistor level using a six-transistor (6T) SRAM cell. Self time techniques have been implemented to optimize the power and access speed of SRAM.