Design Automations of Efficient Complexity Estimation for Digital Integrated Circuit Design

Computer Aided Design (CAD) tools are commonly adopted in the design, synthesis and simulation of digital circuits. Switch-level simulation, logic synthesis, timing analysis and architecture optimizations are essential CAD tools during digital IC design flow. However, the HDL coding, computation complexity and simulation time overhead makes the design turnaround time much longer. This drawback becomes critical in digital circuit high-level synthesis and optimization algorithms when design complexities, such as area cost and delay, need to be efficiently and accurately evaluated within the algorithmic iterations. To address this problem, this paper presents some design automation techniques used during our digital IC design algorithm development, which are helpful to reduce the design and verification turnaround time. One design example using our complexity evaluation model shows that the total algorithm computation time cost has been significantly reduced by 73.1% compared with using the conventional HDL development and simulation cycle. Keywords-Design Automation; Digital IC Design; Circuit Simulation