High-Mobility Nanotube Transistor Memory

A high-mobility (9000 cm2/V‚s) semiconducting single-walled nanotube transistor is used to construct a nonvolatile charge-storage memory element operating at room temperature. Charges are stored by application of a few volts across the silicon dioxide dielectric between nanotube and silicon substrate, and detected by threshold shift of the nanotube field-effect transistor. The high mobility of the nanotube transistor allows the observation of discrete configurations of charge corresponding to rearrangement of a single or few electrons. These states may be reversibly written, read, and erased at temperatures up to 100 K. Decreasing the power required to write and erase memory devices requires either a reduction of the write voltage or a reduction in the number of electrons representing one bit. The former is fundamentally limited by the thermal energy at room temperature, and efforts have focused on the latter. The ultimate reduction, i.e., the storage of a single electronic charge, offers advantages over storing quasi-continuous quantities of charge:1 the Coulomb energy associated with adding additional charges to the storage node can be used to guarantee a discrete charge state,2 and the quantized nature of the charge stored makes the device characteristics less sensitive to the details of the device structure. However, the operation of a single-electron memory at useful temperatures presents two major challenges: the capacitance of the storage node must be small enough that its Coulomb charging energy is significantly larger than the thermal energy at the operating temperature, and the readout device must be sufficiently sensitive to detect a single nearby electronic charge. Efforts to date have focused on floating-gate charge storage nodes either patterned lithographically3-5 or formed serendipitously in a polycrystalline channel.1 Detection of single charges at elevated temperatures has been demonstrated with singleelectron transistors5 or very narrow siliconor polysiliconon-insulator field-effect transistors (FETs).1,3,4 However, single-electron transistors that can operate at room temperature remain extremely difficult to fabricate, and the fieldeffect transistors demonstrated so far have modest mobilities. Here we report on a charge-storage memory using a single semiconducting nanotube FET as the readout. Charge is reversibly injected and removed from the dielectric by applying a moderate voltage (<10 V) across the dielectric between nanotube and substrate. The nanotube FET is ideal as a charge detecting device; it has extremely high mobility (e.g. 9000 cm2/V‚s for the device described here), large geometrical capacitance, and its one-dimensional nature guarantees that local changes in charge density affect the global conductance. In the device reported here, discrete charge states corresponding to differences of a single or at most a few stored electrons are observed and can be written, read, and erased at temperatures up to 100 K, with changes in current of more than 50 nA. This rather crude device demonstrates the significant advantages of nanotube transistors for single-electron or few-electron memories; significant improvement is expected for shorter gate length devices and optimization of the charge storage node. The carbon nanotube in this study was synthesized via chemical vapor deposition over iron nanoparticles at 900 °C, with methane as the feedstock gas,6 on a conducting silicon substrate capped by 500 nm of thermally grown SiO2. Source and drain electrical contacts to the nanotube are made via evaporated Cr/Au electrodes; the conducting substrate acts as a gate electrode. Room temperature and low temperature electrical measurements were carried out with the samples mounted on a cryostat in flowing helium gas. While all data presented here correspond to this device, qualitatively similar behavior was obtained with other semiconducting nanotube devices fabricated in a similar fashion. We begin by discussing the room-temperature characteristics and charge-storage memory operation of our device. Figure 1A shows an atomic force microscope topograph of the device; the nanotube has a length L ) 4.8 μm and a diameter d ) 2.7 nm as determined from the height profile of this image. Figure 1B shows the drain current I as a function of gate voltage Vg with Vsd ) 500 mV applied to the source electrode. The semiconducting nanotube acts as * Corresponding author. Tel: (301) 405-6143. Fax: (301) 314-9465. E-mail: [email protected]. Web: http://www.physics.umd.edu/ condmat/mfuhrer/ NANO LETTERS 2002 Vol. 2, No. 7 755-759 10.1021/nl025577o CCC: $22.00 © 2002 American Chemical Society Published on Web 05/30/2002 a p-type FET, conducting at negative gate voltage and becoming insulating at positive gate voltage, as previously reported.7,8 As the gate voltage is swept back and forth between +10 V and -10 V, a large hysteresis is evident in the I-Vg curves; the threshold gate voltage Vth at which the nanotube begins to conduct is shifted by more than 6 V. Figure 1C demonstrates that this hysteresis may be used as the basis of a stable memory at room temperature. Here the state of the device is read at Vsd ) 500 mV, Vg ) -1 V, and written and erased with pulses of the gate voltage to (8 V. A current of >1μA may be switched. After an initial slow decay (∼ 50 s) the current remains constant; the hold time of the memory exceeds 5000 seconds. We first determine the mobility of our nanotube FET in order to be able to relate changes in conductivity to changes in charge density. The Drude conductivity relation σ ) neμ, where σ is the conductivity, n the linear carrier density, e the electronic charge, and μ the mobility, predicts that the conductivity of the nanotube will grow linearly with carrier density (and hence gate voltage) if the mobility is constant: σ ) Cg(Vth Vg)μ/L, where Cg is the gate capacitance and L the channel length. From the linear portion of the G(Vg) curve, a mobility of the tube μ may be inferred; μ ) (L2/ Cg)dG/dVg. The gate capacitance may be determined directly from low-temperature Coulomb blockade measurements; Cg ) 54 aF, or ∼350 e/V for this device. From the slope9 dG/ dVg ) ∼2.2 μS/V determined from the linear portion of the I-Vg curves in Figure 1B we calculate a hole mobility of ∼9000 cm2/V‚s, greatly exceeding pure silicon (∼450 cm2/ V‚s). This mobility value also greatly exceeds the earlier values reported for laser-ablation-synthesized semiconducting nanotubes8,10 but agrees with other recent results on CVDsynthesized semiconducting nanotubes.11-13 We now discuss the mechanism of charge storage in the nanotube memory device. The threshold shift indicates that a reconfiguration of charge near the nanotube occurs under the application of a gate voltage. This reconfiguration of charge could occur either via the movement of local charges already present in the system, e.g., electrons or ions in the dielectric, or by injection or removal of electrons from the dielectric through the electrodes or nanotube. The “sign” of the hysteresis loop, i.e., positiVe gate voltage increases the threshold voltage, indicates that charges are being injected into the dielectric from the nanotube, similar to a floating gate memory (the opposite sign hysteresis is observed for mobile ions or electrons, for example the “proton memory,”14 which uses mobile hydrogen ions in SiO2). We propose the following mechanism to explain the memory effect in our nanotube devices. Due to the geometry of the device, the electric field is much higher at the nanotube than at the Si/SiO2 interface; for this reason we concentrate on the nanotube as the source of charge injection. The nanotube diameter is small compared to the dielectric thickness, and the geometry may be approximated by a cylindrical capacitor with the nanotube as the center electrode. Because of the small size of the nanotube, the electric field at the nanotube surface is very high: E ) Vg/KRtln(Rg/ Rt) ≈ Vg/23Rt where Rt ) 1.35 nm is the nanotube radius, Rg ) 500 nm is the dielectric thickness, and K ) 3.9 is the dielectric constant of SiO2. Thus the electric field at the nanotube/SiO2 interface for Vg ) 10 V is greater than 0.3 V/nm, comparable to the breakdown field for SiO2 (∼0.25 V/nm), so it is reasonable to expect movement of charge in the dielectric. (Note that “breakdown field” is typically expressed as the potential difference across the dielectric divided by the dielectric thickness, i.e., does not include K, so the typically quoted value of ∼1.0 V/nm for SiO2 translates to an internal electric field of ∼0.25 V/nm). We propose that at these high fields, electrons are easily injected into the dielectric from the nanotube and remain trapped in metastable states until the polarity is reversed. It is notable that a nonvolatile memory based on charge storage in a thick SiO2 gate dielectric was recently reported in organic thinfilm transistors; in this parallel-plate geometry Vg ) 100 V (E ≈ 0.03 V/nm) was sufficient to polarize the SiO2 dielectric.15 The same sign hysteresis was observed as in our case, indicating injection of charge into the dielectric. Other possible mechanisms for charge rearrangement were considered. At such high electric fields the gas around the nanotube may experience corona discharge, and ionized gas could transport charge to the dielectric surface. However, this mechanism would be expected to exhibit a large dependence on the pressure and species of the gas around the nanotube; we found similar operation of the nanotube memory in humid air, dry helium, and dynamic vacuum Figure 1. (A) Atomic force microscope (intermittent-contact mode) topograph of the nanotube device used in this study. The nanotube is the thin, nearly vertical gray line between the two electrodes (dark blocks at top and bottom). Scale bar: 1 micron. (B) Drain current as a function of gate voltage at room temperature and a source-drain bias of 500 mV. As the gate voltage is swept from positive to negative and back a pronounced hysteresis is observed, as indicated by the arrows denoting the sweep direction. (C) Four read/write cycles of the nanotube memory at room temperature. The upper panel shows the drain current at a source-drain bias of 500 mV, while the lower panel shows the gate voltage. The time axis is the same for both graphs. The memory state was read at -1 V, and written with pulses of (8 V. 756 Nano Lett., Vol. 2, No. 7, 2002 (10-3 Torr). It is also possible that the high electric field causes a rearrangement of adsorbates on the nanotube which act as dopants,16 e.g., oxygen; however, it is difficult to explain the observed shift of the threshold voltage from positive to negative simply through rearrangement of electron