Design and Implementation of Multi-bit Flip Flop for Digital Circuits

Power has become a burning issue in modern VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. If a design is given, power consumption can be reduced by replacing some flip-flops with fewer multi-bit flip-flops. However, this procedure may affect the performance of the original circuit. Hence, the flipflop replacement without timing and placement capacity constraints violation becomes a quite complex problem. We have mentioned several techniques, to deal with the difficulty efficiently. Finally, a hierarchical way is used to merge flip-flops. Besides power reduction, the objective of minimizing the total wire length is also considered. According to the experimental results, our design significantly reduces clock power and the running time is very short. In the largest test case, which contains large flip-flops, this design can be used to replace flip-flops and the power reduction can be reduced.