Efficient retiming of large circuits

نویسندگان

  • Naresh Maheshwari
  • Sachin S. Sapatnekar
چکیده

Retiming, introduced by Leiserson and Saxe, is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization and also presented a fast algorithm for minimum period (minperiod) retiming. Since minperiod retiming may significantly increase the number of flip-flops in the circuit, minimum area (minarea) retiming is an important problem. Minarea retiming is a much harder problem than minperiod retiming, and previous techniques were not capable of handling large circuits in a reasonable time. This work defines the relationship between the Leiserson–Saxe and the ASTRA approaches and utilizes it for efficient minarea retiming of large circuits. The new algorithm, Minaret, uses the same basis as the Leiserson–Saxe approach. The underlying philosophy of the ASTRA approach is incorporated to reduce the number of variables and constraints generated in the problem. This allows minarea retiming of circuits with over 56 000 gates in under 15 min.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Eecient Retiming of Large Circuits

| Retiming, introduced by Leiserson and Saxe, is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization, and also presented a fast algorithm for minimum period (minperiod) retiming. Since minperiod retiming may signi cantly increas...

متن کامل

Eecient Minarea Retiming of Large Level-clocked Circuits

Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and e cient techniques for generating it. This results in an e cient minarea ret...

متن کامل

REVERSE: Efficient Sequential Verification for Retiming

We propose a new framework for verifying the sequential equivalence of circuits optimized by retiming. Our approach recognizes the existence of a retiming invariant relating the two circuits, and utilizes that invariant in an induction-based verification paradigm. We prove useful properties about that invariant and present efficient algorithms for computing as well as employing it for verificat...

متن کامل

Retiming Level-Clocked Circuits for Latch Count Minimization

Retiming is a powerful transformation that can minimize the number of memory elements in a sequential circuit under clock period constraints. Recent research has led to the development of extremely fast algorithms for retiming edge-triggered circuits. However, level-clocked circuits have the potential to operate faster and require less memory elements than edgetriggered circuits. This paper add...

متن کامل

An efficient algorithm for performance-optimal FPGA technology mapping with retiming

It is known that most field programmable gate array (FPGA) mapping algorithms consider only combinational circuits. Pan and Liu [22] recently proposed a novel algorithm, named SeqMapII, of technology mapping with retiming for clock period minimization. Their algorithm, however, requires O(Kn log(Kn) logn) run time and O(Kn) space for sequential circuits with n gates. In practice, these requirem...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • IEEE Trans. VLSI Syst.

دوره 6  شماره 

صفحات  -

تاریخ انتشار 1998