Power trends and performance characterization of 3-dimensional integration

Abstruct-3-D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of 2-D, which is widely avowed as the harrier to the continued performance gains in the future technology generations. Therefore, in this paper, we present a stochastic 3-D interconnect model, study the impact of 3-D integration on circuit performance and power consumption. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve the circuit performance. With 3-D integration, a circuit can be clocked at frequencies much higher (double, even triple) than with 2-D. However, we also show that the impacts of vertical wires on chip area and interconnect delay can be limiting factors on the vertical integration of device layers; and that 3-D integration offers limited relief of power consumption.