Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform

Due to recent advances in high dynamic range (HDR) technologies, the ability to display HDR images or videos on conventional LCD devices has become more and more important. Many tonemapping algorithms have been proposed to meet this end, the choice of which depends on display characteristics such as luminance range, contrast ratio and gamma correction. An ideal HDR tone-mapping processor should have a robust core functionality, high flexibility, and low area consumption, and therefore an ARM-core-based system-on-chip (SOC) platform with a HDR tone-mapping application-specific integrated circuit (ASIC) is suitable for such applications. In this paper, we present a systematic methodology for C.-T. Chiu · T.-H. Wang · W.-M. Ke · C.-Y. Chuang · J.-S. Huang · W.-S. Wong · R.-S. Tsay · C.-J. Wu (B) Department of Computer Science, National Tsing Hua University, Hsin-Chu, Taiwan, Republic of China e-mail: [email protected] C.-T. Chiu e-mail: [email protected] T.-H. Wang e-mail: [email protected] W.-M. Ke e-mail: [email protected] C.-Y. Chuang e-mail: [email protected] J.-S. Huang e-mail: [email protected] W.-S. Wong e-mail: [email protected] R.-S. Tsay e-mail: [email protected] the development of a tone-mapping processor of optimized architecture using an ARM SOC platform, and illustrate the use of this novel HDR tone-mapping processor for both photographic and gradient compression. Optimization is achieved through four major steps: common module extraction, computation power enhancement, hardware/software partition, and cost function analysis. Based on the proposed scheme, we present an integrated photographic and gradient tone-mapping processor that can be configured for different applications. This newly-developed processor can process 1,024 × 768 images at 60 fps, runs at 100 MHz clock and consumes a core area of 8.1 mm2 under TSMC 0.13 μm technology, resulting in a 50% improvement in speed and area as compared with previously-described processors.