Implementation of a Low-kickback-noise Latched Comparator for High-speed Analog-to-digital Designs
نویسندگان
چکیده
In traditional comparators especially for ADCs, one serious problem is the kick back noise, which disturbs the input signal voltages and consequently might cause errors at the outputs of the ADCs. In this paper, we will work on a novel ultra low-power rail-to-rail CMOS latched comparator with very low kickback noise for low to medium speed ADCs. This comparator adopts a preamplifier followed by a dynamic latch structure to achieve fast-decision, high resolution as well as reduced kick-back noise. A new adaptive power control (APC) technique is used to reduce the power consumption of the preamplifier. Simulation results would be based on a mixed signal CMOS 0.18μm technology, at a supply voltage of 1.8V.
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