\an Exact Solution to the Transistor Siz- Ing Problem for Cmos Circuits Using Convex Optimization," Ieee Trans. on Computer-aided Design of Run Time (s) Pitch-spacing Min Giss/faf Giss/vaf Lr-based Giss/vaf Lr-based 2 4.2 Wire Sizing and Spacing for Multiple Nets

\Optimal wire sizing and buuer insertion for low power and a generalized delay model," in Proc. 17 problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LR-based optimization algorithm is very eeective and extremely eecient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model 1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work 2]. We believe that our general CH-posynomial formulation and LR-based algorithm can also be applied to other optimization problems in the CAD eld. References 1] J. Cong and L. He, \An eecient approach to simultaneous transistor and interconnect sizing," in Proc. 16 extension of the GISS algorithm to more general capacitance model is beneecial. However, this extension to the general capacitance model is not optimal, and our LR-based optimization algorithm always achieves the best solution. Even compared with the GISS/VAF solution, the delay reduction may be up to 31%. More signiicantly, the LR-based algorithm is 100x faster than the GISS algorithm. Furthermore, it is worthwhile to mention that our LR-based optimization algorithm and implementation is capable to consider the device sizing problem and the wire sizing and spacing problem for multi-source nets, whereas the GISS algorithm is applicable to single-source nets without device sizing. 4.3 Discussions Our experiments show that the identical LR-tight lower and upper bounds are often achieved for most wire segments and transistors, which immediately lead to optimal or near-optimal solutions. Therefore, in our experiments, we simply use the LR-tight lower bound as the nal solution. We noticed that under the table-based model for device, there were a little bit more devices and wires have non-identical lower and upper bounds. However, the table-based device model still gives more delay reduction when compared with the simple device model, even we simply treat the LR-tight lower bound as the nal solution. Meanwhile, identical lower and upper bounds were obtained for almost all wire segments in the experiment using table-based capacitance model. In other words, in terms of the \convergence" of lower and upper bounds, there was no signiicant diierence between the table-based 2D capacitance model with consideration of coupling capacitance, and the simple capacitance model which only uses constant unit-area capacitance and fringe capacitance. When the LR-tight lower and upper bounds do not …