Design Optimization of Discrete-time Single-Loop Sigma-Delta ADCs via Nonideality and Power Analyses

A conventional Σ∆ ADC design approach is a time consuming process and needs much trials and errors. An optimization algorithm for the discrete-time single-loop Σ∆ ADCs design is proposed. Circuit nonideality models are derived in output noise power forms through a systematic circuit imperfection study. A power model is also presented in order to estimate relative power consumption. These models reveal that design parameter variation can potentially affect several noises and errors in different ways, and may change system power consumption. This design complexity is qualitatively summarized into a table. Model completeness allows us to propose an optimization algorithm to search globally for a design parameter combination which meets SNR requirement while minimizing power consumption. Our optimization algorithm is tested against two published design results, and is verified by behavior simulations. Comparisons with behavioral-simulation-based optimization approaches are also made. Key-Words: Sigma delta modulator, noise model, power model, optimization