Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes
نویسندگان
چکیده
In this paper we propose the construction of Spatially Coupled Low-Density Parity-Check (SC-LDPC) codes using a Quasi-Cyclic (QC) algorithm. The QC based approach is optimized to obtain memory efficiency in storing the parity-check matrix in the decoders. A hardware model of the parity-check storage units has been designed for Xilinx FPGA to compare the logic and memory requirements for various approaches. It is shown that the proposed QC SC-LDPC code (with optimization) can be stored with reasonable logic resources and without the need of block memory in the FPGA, and a significant improvement in the processing speed is achieved.
منابع مشابه
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ورودعنوان ژورنال:
- CoRR
دوره abs/1305.5625 شماره
صفحات -
تاریخ انتشار 2013