Unification of Multiple Gated Flip-Flops for Saving the Power Consumption of Register Circuits

Since the clock power consumption in today’s processors is considerably large, reducing the clock power consumption contributes to the reduction of the total power consumption in the processors. Recently, a gated flip-flop is proposed for reducing the clock power consumption of flip-flop circuits. The gated flip-flop employs a clock-gating circuit which cuts off an internal clock signal if the data stored in the flip-flop does not need to be updated. This reduces the clocking power consumption. However, the power dissipated in the clock-gating circuit is still large. For reducing the power dissipated in the clock-gating circuit, this paper proposes a technique for unifying the multiple clock-gating circuits, which reduces the overhead of the clock-gating circuit. Experimental results obtained using an RTL model of a commercial embedded processor demonstrate that our technique reduces the power consumption of register circuits in the processor by 44% on an average and 53% at the best case compared to the register circuits composed of the conventional gated flip-flops.