A low voltage CMOS Pulse Duration Modulator

A CMOS circuit for low voltage Pulse Duration Modulation (PDM) is proposed. This circuit is intended for portable low voltage VLSI system-on-a-chip applications like Hearing aids. The chip operates on a 3V supply and has a power consumption of 0.7mW. The chip occupies an are a of 0.0375mm on a 0.6υm standard CMOS technology. The triangle wave generation is carried out using micro power CMOS comparators. The frequency of the triangular wave is controlled by an external voltage and we can generate triangular waves from 100Hz-510Khz. Introduction As portable-electronics consumers demand smaller devices with longer battery life, designers are looking to replace conventional linear amplifiers with high-efficiency devices. Class D amplifiers provide the balance between efficiency and distortion required by portable devices. Class-D amplifiers use Pulse Duration Modulation PDM (sometimes referred to as pulse width modulation). Many of the existing techniques make extensive usage of resistors or bipolar devices [1,2]. The proposed implementation operates most of the transistors in the sub-threshold region which helps optimize both the voltage supply scaling and the current consumption The outline of the paper is as follows: Section II describes the basic theory behind PDM. Section III discusses the implementation details. Section IV provides the simulation results. The chip performance details are also mentioned here. Section V provides a brief summary. Basic Theory Pulse Duration Modulation means that the original signal Vin at the input is modulated with another signal Vm which has a much higher fixed frequency. The waveform which is used as the carrier wave or modulation signal is normally a triangular signal. The principle is actually quite simple to understand and is explained in Fig.1. The red signal is Vin and the blue signal is the modulation signal Vm. The pulse width modulated signal Vd can be expressed as: Vd = "1" if Vin > Vm Fig 1: PDM signal generation Thus we have a discrete or digital signal which can only be either "0" or "1". This signal has a fundamental frequency equal to that of the modulation frequency fm (the frequency of the modulation signal Vm) but will also contain the input signal and a band of frequency components around the modulation frequency. As shown in Fig. 2 a low pass filter with bandwidth fc is used to reject the switching frequency fm and components around fm thus passing the amplified input signal to the output. Fig 2: Frequency analysis of the PDM signal Implementation The basic block diagram of the circuit is shown below Fig. 3: Block Diagram of the PDM A capacitor is charged and discharged periodically based on the signal that is generated by the comparison of Vcap with voltage levels High and Low as shown in figure 4. Initially the capacitor starts charging and when Vcap becomes higher than High a reset control signal is sent that leads to the discharging of the capacitor. Now when Vcap falls below Low then a set control signal is sent that leads to the charging of the capacitor. This process occurs periodically and a triangular wave thus is obtained. The frequency of this wave can be varied by changing a control voltage. Fig 4: Generation of a Triangular wave The comparator used in this project is a micro-power CMOS comparator. The typical response time is 300ns with an offset voltage of about 15mV. An opamp based topology is used where the input stage of the opamp is determined by the rail to rail requirements. The parallel combination of a ‘p’ and ‘n’ differential pair is chosen. The low speed requirement allows the application of a single stage structure. One condition that must be satisfied to guarantee rail to rail operation is Vdd >= Vgsp + Vgsn + 2. Vdsat Where Vdd is the supply voltage and Vgsp and Vgsn are gate to source voltage of the p and n input pair transistors and the the current sources at the sources of the differential pairs to ensure they are saturated and act as a current source. This condition ensures that the regions of operation of the n and p differential pairs overlap near Vdd/2 and there does not exist a Vdsat is the minimum voltage required across the transistors of gap where none of the pair work. The transistor sizes have been chosen based on different tradeoffs between speed, offset voltages and parasitic resistances. The schematic of the comparator is shown in Fig 4. Fig 5: Schematic of the comparator Simulation results Verifying the PDM output The circuit was designed with the AMI 0.6um CMOS process and was found to occupy an area of 0.0375mm2. The PDM output, the baseband input (5Khz) and the triangular wave of frequency 100Khz is shown in Fig. 6. Note that at the positive peak of the base band signal the PDM pulses have longer high duration while at the negative peak the PDM pulses have longer low duration. Fig 6: Simulated PDM output for a baseband of 5Khz Reconstructing the original signal from the PDM The PDM signal hence obtained was passed through a LPF to check the reconstruction of the original base band signal and we were able to regenerate the original signal as shown in Fig. 7. The delay is because of the buffer which was used for impedance matching. Fig 7: Reconstructed base band signal of 5Khz from PDM signal Triangular wave frequencies The control voltage, Vctrl, of the triangular wave was then varied and the different possible frequencies were noted down. When Vctrl was less than 0.8V we could not generate a triangular wave and as Vctrl was increased to about 3V the triangular wave got clipped and started looking like a pulse with a 95% duty cycle. Table1 shows the different values of frequencies which we obtained. Fig. 8 shows the plot of voltage vs frequency. Table1: Control voltage and corresponding triangular wave frequency Fig 8: Control voltage and corresponding triangular wave frequency Supply Voltage scaling and power Simulations were carried out varying the supply voltage. The ciruit was found to work for voltages as low as 2.8V. The power consumed by this circuit is 0.7mW. Conclusion In this paper, a low voltage PDM circuit was designed using the AMI 0.6um CMOS process. The circuit uses a novel micro power comparator. The circuit occupies a die area of 0.0375mm.The circuit simulations were also shown. Compared to existing PDM solutions, the solution proposed is low power and compact. Table 2 lists some of the chip's features Table 2: Typical results of the modulator Bibliography1. M.C. Killion, E.G Village, "Class D Hearing aidAmplifier", U.S.Patent 4689819,1985 2. H.A. Gurcan, "Class D BiCMOS hearing aid outputamplifier", U.S.Patent 5247581, 1993. 3. F. Serra-Graells, J.L. Huertas,"1V CMOSsubthreshold Log domain PDM", Analog IntegratedCircuits and Signal Processing, 34,183-187,2003 4. M.Baru, O.de Oliveira, F.Silveria, "A 2V rail-to-railmicropower CMOS comparator" 5. F. Serra-Graells, L.Gomez, O.Farres, "A true 1VCMOS log-domain analog hearing-aid-on-a-chip" 6. E.A. Vittoz, "Micropower techniques" Design ofVLSI circuits for Telecommunications and signalprocessing,Eds J.E.Franca and Y. P. Tsividis,Prentice Hall, 1993. 7. F.Silveria, D.Flandre, P.Jespers, "A gm/Id basedmethodology for the design of CMOS analogintegrated ciruits and its application to the synthesisof a silicon-on-insulator micropower OTA", IEEEjournal of solid state circuits. AppendixSchematic and LayoutComplete Chip LayoutComplete Chip Schematic