A Comprehensive Front-End Architecture for the VeriSimple Alpha Pipeline

The performance of a pipelined computer system depends heavily on the degree of Instruction Level Parallelism (ILP) obtained. Pipeline stalling or flushing due to unpredicted or mispredicted branch instructions has become a significant bottleneck to achieving high ILP. A good branch predictor can reduce the number of such stalls and flushes and is therefore critical to the performance of modern day computers. In this project, we designed and implemented a comprehensive front-end architecture to achieve high ILP by experimenting with various branch predictors (including bimodal, local history table, global history table, gShare, and gSelect), a branch target buffer (BTB), an indirect jump predictor (IJP), and a return address stack (RAS). The result is a highly efficient front-end branch predicting architecture. Experimental results show that it can achieve an accuracy of over 95% for conditional branches, and improves the CPI of programs with substantial return instructions and indirect jumps by 20%.