Realization of DUALCORE IBM Power5 Fine Grained Multithreaded Processor

In the present world the computer has become an essential and inevitable part in any field and industry be it in administrative field, science, defense or in any other field. The Processor designed and implemented is typical RISC machines following a 4-stage pipelining having instruction fetch (I-fetch), instruction decode, executing and storing (data memory operations and write back stages) for higher speed operation. The control signals are generated using the hardwired logic for a group of instructions or for particular cases. The processor is implemented with 5-stage fine parallelism controlled using the multithreading concept.This work is implemented using VHDL language. The simulation and synthesis of the implemented design is carried out using XILINX ISE tool. Further route and placement and Floor planning is to be carried out using Xilinx FPGA editor and Floor Planner respectively.