TID Damage and Annealing Response of 90 nm Commercial-Density SRAMs

We characterize the TID resilience and annealing response of high-density SRAMs, fabricated in 90 nm commercial processes. Results demonstrate intrinsic SRAM hardness at 300 krad(Si), but also reveal several orders of magnitude increase in leakage current at 1 Mrad(Si) of exposure, with recorded critical functionality failures. However, the technology is shown to be very responsive to temperature treatments as all chips recover to pre-rad leakage levels after 5 hours at 150C with fully regained functionality. Finally, consecutive exposure/anneal cycles reveal a drastic improvement in TID resilience as SRAMs that did undergo at least one postrad anneal stayed fully functional up to the strategic TID level of 2 Mrad(Si) once re-exposed. The gained resilience is attributed to negative interface trapped charge build-up along the STI walls: it progressively turns OFF the channel of parasitic transistors responsible for TID-induced leakage paths creation.