Polynomial-time Techniques for Approximate Timing Analysis of Asynchronous Systems a Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

As designers strive to build systems on chips with ever diminishing device sizes, and as clock speeds of gigahertz and above are being contemplated, the limitations of synchronous circuits are beginning to surface. Consequently, there has been a renewed interest in asynchronous design techniques that use judicious timing assumptions to obtain fast circuits with low hardware overhead. However, the correct operation of these circuits depend on certain timing constraints being satisfied in the actual implementation. Since statistical variations in manufacturing conditions and operating conditions result in uncertainties in component delays in a chip, it is important to analyze asynchronous systems with uncertain component delays to check for timing constraint violations and to determine sufficient conditions for their correct operation. Unfortunately, several timing analysis problems are computationally intractable when component delays are uncertain but bounded. This thesis presents polynomial-time techniques for approximate timing analysis of asynchronous systems with bounded component delays. Although the algorithms are conservative in the worst case, experiments indicate that they are fairly accurate in practice. Three important problems in asynchronous timing analysis are addressed. First, a polynomial-time algorithm for computing bounds on signal propagation delays from each primary input to each gate in a combinational circuit is described. This has applications in determining input timing constraints for correct operation of asynchronous circuits. To improve the accuracy of simulation, a polynomial-time reconvergent fanout analysis technique is also proposed. As an application, a timing analysis tool for a class of asynchronous circuits is presented. Experiments indicate that the proposed algorithm is efficient and fairly accurate in practice. Next, the problem of computing bounds on time separation of events in asynchronous