Five-Transistor SRAM Cell with Improved Write Capability

In this paper, we propose a five-transistor (5T) static random access memory (SRAM) that can be read and written reliably with the assistance of read/write circuits. The read/write circuits include a voltage control circuit, a pre-charging circuit and a standby start-up circuit. The voltage control circuit is connected to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, in a write mode, the issue concerning the difficulty of writing a logic ‘1’ can be avoided. In a read mode, the reading speed can be increased without incurring unnecessary power consumption. In a standby mode, leakage current can be reduced effectively. In addition, each column memory cells set up a pre-charging circuit, and each pre-charging circuit is connected to the bit line BL of the corresponding column memory cells. Moreover, the standby start-up circuit design enables the single-port SRAM to quickly switch to the standby mode, which effectively enhances the standby performance of the single-port SRAM.