Formal Definition of an Abstract Vhdl'93 Simulator by Eaamachines

We present a rigorous but transparent semantic deenition for VHDL corresponding to the IEEE VHDL'93 standard. Our deenition covers the full behavior of signal and variable assignments as well as the behavior of the various wait statements including delta, time, and postponed cycles. We consider explicitly declared signals, ports, local variables, and shared variables. Our speciication deenes an abstract VHDL'93 interpreter which comes in the form of transition rules for evolving algebra machines EAAMachines 155. It faithfully reeects and supports the view given in the IEEE VHDL'93 standard language reference manual. The deenition can be understood without any prior formal training. We outline our deenition running the VHDL program which is given in the preface of this volume.