Built-in Adaptive Test and Calibration of DAC

Linearity is a critical measurement for overall performance of digital-to-analog converters (DAC) in mixed-signal system-on-chips (SoCs). Device parameters become more difficult to control due to variations from fabrication process with deep sub-micron technology. Such parameters also continue to degrade after fabrication as time elapses. Process variations of DACs are major source of non-linearity errors and will seriously keep degrading performance of SoCs. In this paper, we propose a novel digital post-fabrication variation-tolerant solution to reduce nonlinearity error of on-chip high-resolution DAC by digital signal processor which is generally available on the SoC. The nonlinearity error will be measured by a high-linear sigma-delta ADC and the DAC will be adaptively characterized to obtain a best matching polynomial. Then the non-linearity error can be corrected using the polynomial through a low-resolution dithering DAC. Simulation results show that a sigma-delta modulator with effective number of bits (ENOB) equivalent to a 17-bit ADC. A 6bit dithering DAC is sufficient to calibrate a 14-bit high-resolution on-chip DAC and reduce the maximum non-linearity error from 3 LSB to 0.5 LSB. The proposed solution is technology independent and can be applied to any digitally controllable mixed-signal device for various process variation-tolerant applications.