How Programmable is Reconfigurable Hardware? : A Design Model for Reconfigurable Architectures
نویسندگان
چکیده
With large-capacity FPGAs, such as the Xilinx Virtex family, complex systems can now be constructed from reconfigurable hardware, and sophisticated designs are more easily implemented through C-language hardware compilers, such as Handel-C [1]. However, improved language support is not enough, as effective system design needs structured methods and high-level design support, which a language by itself cannot provide. This paper address the need for additional application development support by proposing a system-level asynchronous model, based on CSP (Communicating Sequential Processes) [2], and implementing an FPGA runtime environment allowing user-level ‘task’ objects to communicate via Handel-C channels.
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