FPGA Implementation of a 4×4 Vedic Multiplier
نویسندگان
چکیده
this paper portrays for the design of an area efficient 4×4 Vedic Multiplier by using Vedic Mathematics algorithms. Out of the 16 sutras the Urdhva -Tiryakbhyam sutra is being discussed and implemented because this sutra is applicable to all cases of algorithm for n×n bit numbers and gives minimum delay for multiplication of all types of numbers. The complete multiplier is designed using VHDL language. The design is simulated using Xilinx ISE project navigator and the functionality of the circuit is verified by generating test-bench waveform. The proposed multiplier in this paper can be used in many real-time signal and image processing applications.
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