Behavioural Vhdl Description Based Synthesis of Self-checking Circuits
نویسندگان
چکیده
This paper demonstrates an experimental implementation of a design method for embedding fault tolerance capabilities into high level digital system models. The method starts with a standardized behavioural level system description and systematically transforms it to an implementation-level circuit design with fault tolerant parts built in. The transformation process aims to keep the changes made in the model transparent from the viewpoint of the designer, in order to maintain compatibility between the original system model and to minimize the manual interaction needed to implement fault tolerance.
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