New design criterion for high-order DACs

Stable high-order delta-sigma DACS

Stability analysis of high-order delta-sigma loops is a challenge. In this brief, a sufficient design criterion is presented for highorder multibit error-feedback DACs which are especially suitable for high-speed operation. This analytical criterion might be too conservative, but it allows the design of stable, robust, and high-resolution deltasigma DACs. Both analytical and numerical analysis ...

Compact low-power calibration mini-DACs for neural arrays with programmable weights

This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion opera...

Design of Continuous-Time Σ∆ Modulators with Sine-Shaped Feedback DACs

This work presents a general method to design continuous-time Σ∆ modulators with sine-shaped feedback DACs. A discrete time to continuous time transformation technique is used to compute the continuous-time loop filter coefficients, taking into account the sinusoidal feedback. Examples of high order lowpass and bandpass continuous-time Σ∆ modulators are given as an illustration for the proposed...

A Deterministic Dynamic Element Matching Approach for Testing High Resolution ADCs Using Low Accuracy DACs (Design Number: 68091)

Wideband Modem Design Using FPGAs

1. ABSTRACT New waveform requirements are pushing the limits of traditional modem design techniques. Fortunately, modern Digital-to-Analog Converter (DAC) and Analog-to-Digital Converter (ADC) can achieve sampling rates in the GHz range. These new DACs and ADCs allow designers to directly synthesize channels that have bandwidths of more than 500 MHz+; allowing either wideband or multi-channel m...