Simulation of Single-Electron/CMOS Hybrid Circuits Using SPICE Macro-modeling
نویسندگان
چکیده
Recently, there has been great progress in the fabrication of various nano-devices utilizing silicon ULSI processing techniques [1]. Reliable room temperature operations have been demonstrated in a silicon single-electron quantum-dot transistor [2], a silicon selfassembled quantum-dot transistor [3], and various types of single-electron memory cells [4,5]. However, these single electron or quantum devices usually have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. One possible solution to overcome this problem is to build hybrid circuits consisting of single electron transistors (SETs) and CMOS interfaces [6] and in this case, simultaneous simulations of single electron circuits (SECs) and CMOS circuits are required for efficient circuit design and analysis. Usual SEC simulators such as MOSES [7], SIMON [8], KOSEC [9], and SENECA [10] are not compatible with SPICE and the only way of simultaneous simulation of hybrid circuit is to insert SEC simulation capabilities into SPICE source code. On the other hand, recently developed SPICE macro-modeling technique [9,11] is based on SPICE macro code and can be conveniently used for hybrid circuit simulation without having to modify the SPICE source code. In this paper, the SPICE macro-modeling of SETs has been successfully applied to the simulation of singleelectron/hybrid circuits. Several hybrid circuits such as an SET-NMOS pair and a single electron NOR-gate with CMOS buffers have been simulated and efficient interface characteristics are demonstrated.
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