A non-enumerative path delay fault simulator for sequential circuits

W e extend the path status graph (PSG) method of delay faul t simulation to sequential circuits. By devising a layered PSG and restricting the number of timeframes over which a fault mus t be detected, we preserve the non-enumerative nature of the simulation algorithm. T h e program is capable of simulating a wide variety of circuits (synchronous, asynchronous, multiple-clock and tri-state logic.) Both rated and variable clock modes, as well as robust, non-robust or funct ional sensitization detection options, are available. The simulation can be stopped and restarted through a checkpointing facility. The program can target any given list of paths. This path list can also be generated b y the program based o n user-selectable criteria (all paths, longest paths, paths between certain 1/0 pairs, etc.) User reports include a histogram of path coverage versus path length. Detected and undetected path data remain implicit in the PSG and can be retrieved through post-processing commands. Due to i ts non-enumerative nature, the program can process mos t production level digital logic circuits. the path-delay fault, assumes that delays of a chain of gates (a path) cumulatively causes a failure. The gatedelay fault model is often regarded as unrealistic since it assumes a large delay for a single faulty gate. The pathdelay fault model, on the other hand, has the shortcoming that the number of paths in a circuit can be exponential in the number of logic gates [l]. Recent work has shown the possibility of nonenumerative simulation techniques for path delay faults [2]. Although exact simulation for combinational circuits has been demonstrated, such methods have no straightforward extensions to sequential circuits. In this paper, we extend the path status graph (PSG) technique for non-enumeratively simulating path delay faults in sequential circuits. The testability of all paths is recorded in a graph by tagging the path edges. Although in the worst case the method can be as memory intensive as any enumerative approach, experiments show that this rarely happens. This work now provides a path delay fault simulation capability in Bell Labs’ Gentest environment [3]. 2 Background