An Advanced 3D Frame Buffer Memory Controller

This paper details the design of an advanced 32 bit 3D frame buffer memory controller for a 3D Graphics Raster Processor called TAYRA [1]. This memory controller is designed to provide a performance of 33 MPixelsls for read and write cycles, 4 GPixelsls for block write, and 16.5 MPixelsls for read, modify, write cycles (with a pixel size of4 bytes). This performance is without any interleaving. It has several control modes: S3 shared frame buffer protocol compatibility [2], stand alone 3D buffers, multiplexed 2DI3D buffers, and others. Further, our 3D memory controller is designed to control DRAM, VRAM and WRAM, and EDO versions of these memories. Also, we support up to 4 screen buffers, 16 MBytes of screen memory, and many combinations of memory organisations up to 1600x1280.