Bit-Level Pipelinable General and Fixed Coefficient Digit-Serial/Parallel Multipliers Based on Shift-Accumulation
نویسندگان
چکیده
In this work we introduce a novel approach to digit-serial/parallel multiplication. This general class of multipliers is based on shiftaccumulation which also makes the approach suitable for implementation of shift-accumulators in distributed arithmetic. As a variable in the design process, the maximal number of cascaded fulladders can be selected. Thus, it is possible to as a special case obtain a bit-level pipelined multiplier. Both general and fixed coefficient multiplication is considered. The hardware complexity is low compared with other approaches.
منابع مشابه
Switching Activity in Bit-Serial Constant-Coefficient Serial/Parallel Multipliers
Bit-serial architectures have the advantage of high throughput, area efficient multipliers. These multipliers are implemented using shift-add operations [1], with full adders and D flip-flops as building blocks. Multiplication with a constant fixed-point coefficient is commonly used in digital signal processing (DSP) circuits, such as digital filters [2][3]. The design of a constant-coefficient...
متن کاملDesign and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL
A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of func...
متن کاملDesign and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL
A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. 
The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of fu...
متن کاملBit-Serial and Digit-Serial GF(2) Montgomery Multipliers using Linear Feedback Shift Registers
This work presents novel multipliers for Montgomery multiplication defined on binary fields GF(2). Different to state of the art Montgomery multipliers, this work uses a Linear Feedback Shift Register (LFSR) as the main building block. We studied different architectures for bit-serial and digit-serial Montgomery multipliers using the LFSR and the Montgomery factors x and xm−1. The proposed mult...
متن کاملBit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers
This work presents novel multipliers for Montgomery multiplication defined on binary fields GF(2). Different to state of the art Montgomery multipliers, this work uses a Linear Feedback Shift Register (LFSR) as the main building block. We studied different architectures for bit-serial and digit-serial Montgomery multipliers using the LFSR and the Montgomery factors x and x. The proposed multipl...
متن کامل