A handy systematic method for data hazards detection in an instruction set of a pipelined microprocessor
نویسنده
چکیده
handy systematic method for enumerating all possible data dependency cases that could occur between any two instru c-tions that might happen to be processed at the same time at different stages o f the pipeline. Given instructions of the instruction set, specific information about operands of each instruction and when an instruction reads or writes data, the method could be used to enumerate all possible data hazard cases and to determine whether forwarding or stalling is suitable for resolving each case.
منابع مشابه
A Correctness Model for Pipelined Microprocessors
What does it mean for an instruction pipeline to be correct? We recently completed the speciication and veriication of a pipelined microprocessor called Uinta. Our proof makes no simplifying assumptions about data and control hazards. This paper presents the spec-iication, describes the veriication, and discusses the eeect of pipelining on the correctness model.
متن کاملOn Proving with Event-B that a Pipelined Processor Model Implements its ISA Specification
Microprocessor pipelining is a well-established technique that improves performance and reduces power consumption by overlapping instruction execution. Verifying, however, that an implementation meets this ISA specification is complex and time-consuming. One of the key verification issues that must be addressed is that of overlapping instruction execution. This can introduce hazards where, for ...
متن کاملTerm-Level Verification of a Pipelined CISC Microprocessor
By abstracting the details of the data representations and operations in a microprocessor, term-level verification can formally prove that a pipelined microprocessor faithfully implements its sequential, instruction-set architecture specification. Previous efforts in this area have focused on reduced instruction set computer (RISC) and very-large instruction word (VLIW) processors. This work re...
متن کاملExploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors1
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2][3] to the verification of pipelined microprocessors with very large Instruction Set Architectures (ISAs). Abstraction of memory arrays and functional units is employed, while the control logic of the processors is kept intact from the original gate-level designs. PEUF is an extension of the logi...
متن کاملInstruction Set Commutivity
We present a state property called congruence and show how it can be used to demonstrate commutivity of instructions in a modern load{store architecture. Our analysis is particularly important in pipelined microprocessors where instructions are frequently reordered to avoid costly delays in execution caused by hazards. Our work has signiicant implications to safety and security critical applica...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- CoRR
دوره abs/1203.0787 شماره
صفحات -
تاریخ انتشار 2012