Reduction of Static Power Dissipation in Adiabatic Combinational Circuits Using Power Gating MTCMOS
نویسندگان
چکیده
This paper proposes a method to reduce static power consumption in Adiabatic logic circuits based on Complementary Pass transistor Adiabatic Logic (CPAL) operated by two phase power clocks. We are applying power gating MTCMOS technique to reduce static power consumption in CPAL circuits. We tested MTCMOS power gating technique on 4-bit ripple carry adder to observe effect of static power reduction on two phase CPAL combinational circuits. On an average we are saving 48% of static power by using power gating MTCMOS technique to CPAL circuits and the static power is constant with frequency in power gating MTCMOS CPAL circuits. All the circuits are verified using Cadence 180nm technology with Spectre simulator.
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