Post-silicon Timing Diagnosis under Process Variations

With continuous technology scaling, process variations have become a major factor affecting the performance of VLSI designs. Even a small degree of variation in device parameters may amplify at the system level, resulting in significant deviations in circuit timing. Post-silicon timing diagnosis addresses the issues of estimating the timing of each fabricated chip. It aims to identify individual paths that fail to meet their required timing constraints, despite the lack of access to the inside of the chip and the limitation to at most a few thousand I/O pins from which to reason about the timing behavior of billions of nano-scale components in a circuit. The lack of both access to and knowledge of individual process variations inside a fabricated chip causes post-silicon timing diagnosis to be timing-consuming and expensive. In this thesis, we propose a framework for automating post-silicon timing diagnosis under process variations. First, our goal is to characterize the timing of the fabricated chips in order to isolate the failing paths in “slow” chips that fail to operate correctly at the required frequency. Moreover, our framework localizes those segments on the failing paths that show more deviation in their post-silicon delays. The first step in our proposed framework is to identify the statistically-critical paths under process variations. These are the paths that have the highest probability