Testability Optimizations for A Time Multiplexed CPLD Implemented on Structured ASIC Technology
نویسندگان
چکیده
Multi-context dynamic reconfigurable architectures can use of both spatial and temporal aspects of logic capacity. Gaining logic capacity by reusing hardware with time multiplexing techniques requires controlling logic using small distributed memories. This can create testability problems for dynamic reconfigurable architectures. In this paper we are analysing the test coverage loss and proposing a test extension for a CPLD like dynamic reconfigurable architecture. The proposed solution is implemented in structured ASIC technology and helps in regaining the test coverage with no area and timing penalty.
منابع مشابه
Lackey for IBM ASIC products by J . J . Engel
The IBM ASIC design methodology enables a product developer to fully incorporate the high-density, high-performance capabilities of the IBM CMOS technologies in the design of leading-edge products. The methodology allows the full exploitation of technology density, performance, and high testability in an ASIC design environment. The IBM ASIC design methodology builds upon years of experience wi...
متن کاملParity Error Detection in Embedded System
Abstract : In this article we describe one suitable approach that enables the designer to insert a boundary-scan and built-in-self-test concepts, as typical designfor-testability techniques in system-on-chip and multichip module embedded system design, for fault-effects detection. For transient error detection implementation of parity error detection into a 36-bit bus transceiver circuit (32-bi...
متن کاملA Novel Shift and Add Algorithm for Low Power and Area Efficient Fir Filter
High-speed DSP systems are increasingly being implemented on FPGA hardware platforms. This trend is being fuelled by insurmountable ASIC project costs and the flexibility and reconfigurability advantages of FPGAs over traditional DSPs and ASICs, respectively. Very recently, Structured ASIC technology has yielded lower cost solutions to full custom ASIC by predefining several layers of silicon f...
متن کاملModular approach for an ASIC integration of electrical drive controls
VLSI circuits design allows today to consider new modes of implementation for electrical controls. However, design techniques require an adaptation effort that few designers, too accustomed to the software approach, provide. The authors of this article propose to develop a methodology to guide the electrical designers towards optimal performances of control algorithms implementation. Thus, they...
متن کاملASIC Design of Butterfly Unit Based on Non-Redundant and Redundant Algorithm
Fast Fourier Transform (FFT) processors employed with pipeline architecture consist of series of Processing Elements (PE) or Butterfly Units (BU). BU or PE of FFT performs multiplication and addition on complex numbers. This paper proposes a single BU to compute radix-2, 8 point FFT in the time domain as well as frequency domain by replacing a series of PEs. This BU comprises of fused floating ...
متن کامل