Advanced CMOS ULSI Circuits

Analog Design in ULSI CMOS Processes

This paper discusses some of the advantages and of the disadvantages of using a CMOS process in the 180 – 100 nm range for the design of analog blocks in mixed-mode integrated circuits.

AES and Related Techniques for Yield Improvement, Metrology and Development Support of ULSI Circuits Manufactured in 28nm CMOS Technology

A Novel Design of SET-CMOS Half Subtractor and Full Subtractor

Single Electron transistor have high integration density, ultra-low power dissipation, ultra-small size, unique coulomb blockade oscillation characteristics which makes an attractive technology for future low power VLSI/ULSI systems. The Single Electron Transistor have extremely poor driving capabilities so that direct application to practical circuits is a yet almost impossible, to overcome th...

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a...

Estimation of On-Chip Simultaneous Switching Noise in VDSM CMOS Circuits

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped model. The waveform describing the SSN voltage is quite close to the waveform obtained from SPICE. The peak value of the simultaneo...