Current Frame Processor Tree with p ’ leaves Previous Frame Module p ’ Data

Hierarchical block matching is an eecient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architec-tures for implementing hierarchical block matching. The rst architecture is memory-eecient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires signiicantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures.