Simulated Annealing based VLSI Circuit Partitioning for Delay Minimization
نویسنده
چکیده
In this work two way partitioning of a circuit represented as a graph, is made using simulated annealing procedure and delay between the partitions is minimized. The various parameters used in the annealing process like initial temperature, cooling rate, and the threshold, given as a number of calculations , are changed and its influence on the delay between the partitions is discussed. Procedure was tested on an example with a 102 components connected by 103 nets. Substantial improvement in delay is obtained over the initial circuit delay proving the effectiveness of proposed method. Key-Words: Delay;partitioning;netlist;simulated Annealing,VLSI
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