Toward Testing Realistic Fault Behavior: Delay Fault Test

5.1 Introduction The increasing circuit operating frequencies and demands for low cost and high quality require that the temporal correctness of the circuit can be guaranteed. For high performance circuits with aggressive timing requirements, small process variations can lead to failures at the design clock rate. These defects can stay un-detected after at-speed or stuck-at-fault testing. Delay testing can detect these defects. In this chapter we describe the fault models and testing schemes designed to detect delay defects. We do not intend to give a comprehensive review on this subject. Instead we focus on some selected issues related to delay testing of sequential circuits. Two fault models are commonly used for timing defects: gate delay model [38][39] and path delay model [35][24]. Gate delay fault model assumes that the fault affects only one gate or one interconnect in the circuit. Under path delay fault model the circuit is considered faulty if the delay of any of its paths exceeds a specified limit. Both of these models have their advantages and disadvantages. Under the gate delay model the number of faults is linear in the number of gates. However, gate delay model may fail to detect delay faults which are result of the sum of several small delay defects. Path delay fault model can detect small distributed delay defects caused by statistical process variations. However, in the path delay fault model the number of faults is, in the worst case, exponential in the number of gates in the circuit. The problem can be alleviated by selecting only a small subset of paths for testing and/or by applying resynthesis techniques for reducing the number of paths in a circuit [30][19]. In order to test delay defects an input vector pair, V = , needs to be applied to the combinational portion of the circuit. The first vector initializes the circuit, while the second causes the desired transitions. The signal values after application of the first vector are assumed to be stabilized before the second vector is applied. After a clock cycle from the time when the second input vector was applied, the values on the primary outputs are observed and compared to the prestored response of a fault free circuit to determine if there is a defect. Most of the delay testing research has concentrated on testing combinational circuits. Testing delay faults in sequential circuits is significantly …