Fault-tolerant system design using novel majority voters of 5-modular redundancy configuration

Introduction: The highly reliable systems are often used in most critical applications like Bank transactions, Defense communications, Aerospace applications, etc. The loss will be enormous if these systems fail in the field, i.e., during the operating time. The circuit designers keep researching to build intelligent systems with reliability improvement by adding redundancy like hardware, software, information and time. In this study, the hardware redundancy is used to improve the reliability of the system. Methodology: The Triple Modular Redundancy (TMR) which can tolerate one error is the most common technique used to mitigate errors in the field of microelectronics reliability. This study primarily focuses on new majority voters of a 5MR system which can tolerate two errors for the betterment of reliability. The optimization of the majority function of a 5-MR system is the key to the proposed ideas. Results & Conclusion: Simulation results show that the first proposed majority voter offers a lower delay as 0.390 ns as compared to 0.460 ns by existing majority voter and less layout area as 367. 8 μm 2 . The secondly proposed majority voter dissipates less power as 7.633 μW as compared to 13.211 μW by the existing majority vote. It is also shown that the proposed majority voters offer a better figure-of-merit as compared to the current majority voting architecture by implementing them with the industry standard benchmark circuits.