A Review of SOI Technology and its Applications

Substrate engineering [1] has enabled the industry to overcome many of the limitations encountered by traditional scaling. As a result, device architecture and engineered substrates have become strongly coupled, a coupling that is growing stronger as the IC industry moves to the 32 nm technology node and beyond. Substrate engineering started in earnest with the industry transition to SOI wafers in the late ‘90s. SOI substrates made possible increasing the drive current while simultaneously reducing parasitic leakage and capacitance, thus improving IC performance and reducing power consumption. SOI has allowed the IC industry to develop superb solutions for high performance logic [2]. A review of applications driving high performance devices is presented here. The SOI architecture for low power application is also discussed. Ultra-Thin Body (UTB) device architecture is extensively investigated to suppress the short channel effects (SCE) for scaling gate length beyond 30 nm and to lower the sub-threshold leakage as projected by the International Technology Roadmap for Semiconductors (ITRS). The combination of high mobility channels and UTB SOI devices is most appealing for high density, high performance and low power applications. The future nodes are driving numerous substrate solutions. Today’s partially depleted (PD) transistor architecture implemented for high performance processors may evolve into a fully depleted (FD) approach with planar single gate transistors or with multiple gate (FinFET, TriGate) structures. SOI substrates are also essential to RF circuits, Si-based Optoelectronic devices, MEMS, high voltage and Smart Power circuits, back-side illuminated image sensors, and to other emerging applications [3].