FULL ON-CHIP CMOS LOW DROPOUT VOLTAGE REGULATOR WITH -41 dB AT 1 MHZ FOR WIRELESS APPLICATIONS

A high PSRR full on-chip and area efficient low dropout voltage regulator (LDO), exploiting the nested miller compensation technique with active capacitor (NMCAC) to eliminate the external capacitor and improve the high performance. A novel technique is used to boost the important characteristic for wireless applications regulators PSRR. The idea is applied to stabilize the Low dropout regulator. The proposed regulator LDO works with a supply voltage as low as 1.8 V and provides a load current of 50 mA with a dropout voltage of 200 mV, the PSR of LDO is -60 dB at a frequency of 60 KHz and -41dB at a frequency of 1 MHz. It is designed in 0.18 μm CMOS technology and the active area on chip measures 0.043 mm. Keyword: Low Dropout Regulator (LDO); MOSCAP; NMCAC; Active Feedback; High PSR; System On Chip.