Feed-forward voltage in CMOS pinned photodiodes

CMOS image sensors have become very popular in low cost imaging devices. In order to realize images of high quality, the image sensors need to have a high resolution, be able to achieve a high Signal-to-Noise ratio (SNR) and have a wide dynamic range. To increase the spatial resolution of the image sensors, the pixel size has been scaling down allowing integration of more pixels in a given die area. On the side, this scaling process reduces the potential barrier separating the charge generation centers from collection centers in modern CMOS photodiodes. This reduces the charge handling capacity of the photodiode well as well. Electrons contained within a well possess thermal energy, and thus acquire random thermal velocities. A sufficient barrier is thus needed to prevent the overflow of electrons when the photodiode potential well is full. In classical CCDs it was found that the minimum barrier needed to hold the electrons in the photodiode well is around 0.4V-0.6V. However the charge handling capacity of the CMOS pinned photodiodes are not well studied. In this paper, the minimum barrier potential needed in a pinned photodiode and the feed-forward of electrons are presented for dependencies on variations in photodiode geometry, temperature and bias voltages.