A New Scalable DSP Architecture for Mobile Communication Applications

Digital Signal Processors (DSPs) are employed in all elds of mobile communication applications, e.g. in speech, audio, modem, video, or graphic processing. Due to diierent processing requirements, today, for each application diierent DSPs have to be employed. Thus, in contrary to existing DSP solutions, our work is targeted towards designing expandable and customizable DSP architectures. To achieve this goal, DSP memory and register les must be scalable. Instead of taking large register les or matrix memories our DSP architecture employs a group memory. In this memory several data elements are treated as one group and share one common address. This allows us to keep the address generation unit simple. By employing a register le which is optimized for digital signal processing algorithms our DSP architecture becomes fully scalable. Using this architecture DSP design can be substantially facilitated and design cycles can be widely reduced. The usefulness of this paradigm is demonstrated by showing its performance by means of major DSP algorithms such as lters or FFTs.