Capacitance variability of short range interconnects

End of the roadmap integrated circuit interconnects suffer from capacitance variability due to line edge roughness (LER), significantly impacting overall circuit performance. We forecast the capacitance variability of short range interconnects with realistic line edge roughness at the upcoming 45, 32, and 22 nm technology nodes using a fast TCAD capacitance tool. Capacitance variability is layout sensitive and worsens with reduction in feature size, and together with the increasing device variability requires inclusion in statistical models of standard cells from the 45 nm node onwards. If LER does not improve then, for example, by the 22 nm node, short parallel lines on metal 1 are predicted to have 12% variability and, depending on layout, SRAM bit line capacitance 7% variability.